1. Technical Field
The present invention relates generally to a memory system and a method for the error correction of memory, and more particularly to a memory system and a method for the error correction of memory that can improve the reliability and performance of the memory system.
This application claims priority of Korean Patent Application No. 10-2015-0138269 filed on Sep. 30, 2015, the entire contents of which is incorporated herein by reference.
2. Description of the Related Art
Recently, as the process scaling of Dynamic Random Access Memory (DRAM) continues to increase, a tendency for an error to occur in a memory cell increases. DRAM is memory that has finite data retention characteristics. Accordingly, as the process scaling of DRAM increases, the reliability of data stored in a memory cell decreases.
Furthermore, as the cell failure rate increases, conventional solutions, such as the addition of reserved repair resources and reliance on error-correcting code (ECC), have problems in that high area overhead, the disadvantage of the latency of data coding, and interference between in-DRAM ECC (ECC within a DRAM chip) and rank-level ECC (ECC across DRAM chips) occur.
As a result, there is a need for technology that is capable of overcoming the above-described problems.
Meanwhile, the above-described background technologies correspond to technical information that has been possessed by the present inventor in order to devise the present invention or that has been acquired in the process of devising the present invention, and cannot be necessarily viewed as well-known technology that had been known to the public before the filing of the present invention.